DAC0=0, ADC0=0, PIT=0, SPI1=0, SPI0=0, RTC=0, FTF=0, DMAMUX=0, TPM2=0, TPM0=0, TPM1=0, TRNG=0
System Clock Gating Control Register 6
| FTF | Flash Memory Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| DMAMUX | DMA Mux Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| TRNG | TRNG Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI0 | SPI0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI1 | SPI1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PIT | PIT Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| TPM0 | TPM0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| TPM1 | TPM1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| TPM2 | TPM2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ADC0 | ADC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| RTC | RTC Access Control 0 (0): Access and interrupts disabled 1 (1): Access and interrupts enabled |
| DAC0 | DAC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |